Layout versus Schematic (LVS) Debug

By Chirag Rajput, Nilay Mehta, Chirag Maniya (eInfochips)

What is LVS?

In ASIC physical implementation, once layout is generated, it must follow all the design rules for successful manufacturing and must match the schematic of the required design. To ensure this in physical verification, Design Rule Check (DRC) is carried out to check whether the layout follows the rules for fault-less manufacturing or not. This DRC checks provide good manufacturing yield and prevents faults during manufacturing, however it does not ensure the correctness of the layout. It needs to be ensured that, the physical implementation of the design is the same as the schematics of the design. For this, the electrical circuit of layout netlist is compared against the schematic netlist, which is known as Layout versus Schematic (LVS).

Here IC Validator and IC Compiler-II (SYNOPSYS) tools are used for LVS runs and PnR.

Figure 1: LVS

As shown in the above figure, LVS is a comparison between layout, which is represented by GDS and schematic that is generated by the tool using verilog netlist.

Input files for LVS in ICV tool are listed below:

  • GDS (layout stream file): It is used by the LVS tool to generate layout netlist by extraction, which is used for LVS comparison.
  • Schematic netlist: It is used as a source netlist for LVS comparison.
  • Rule deck file: Rule deck file consists of required instructions and files to guide tool for performing LVS. This rule deck file also contains a layer definition, which is useful for extraction.
  • Equivalence file: It is used by the tool for ICV LVS comparison and it consists of cell pairs, which is made-up of one from the layout netlist and another from the schematic netlist.

LVS Flow

LVS flow is mainly consisting of extraction and comparison of layout netlist and schematic netlist. LVS flow is depicted in the figure-2. ICV has nettran utility for translation of input verilog netlist to ICV schematic netlist, which is further useful for…

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